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ICs for Communications
Primary Rate Access Clock Generator and Transceiver PRACT PEB 22320 Version 2.1
Data Sheet 04.95
PEB 22320 Revision History Previous Version: Page 10 14 16 17 18 23 24 28 29 31 32, 33
Current Version: 04.95 05.93 Subjects (changes since last revision) Architecture of the PRACT Input Jitter Specification Jitter Attenuator Block Diagram Clock- and Synchronization Table Jitter Attenuation Characteristics Master/Slave Selection Reset Delay Times DC Characteristics Recommended Oscillator Circuits Crystal Tuning Range
Data Classification Maximum Ratings Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Characteristics The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 C and the given supply voltage. Operating Range In the operating range the functions given in the circuit description are fulfilled. For detailed technical information about "Processing Guidelines" and "Quality Assurance" for ICs, see our Product Overview "ICs for Communications"
PEB 22320
General Information Page
Table of Contents 1 1.1 1.2 1.3 2 2.1 2.1.1 2.1.2 2.1.3 2.1.4 2.2 2.2.1 2.2.2 2.3 2.4 2.5 2.6 2.7 2.8 3 3.1 3.1.1 3.1.2 3.2 4 4.1 4.2 4.2.1 4.2.2 4.3 4.4 4.5 4.6 4.6.1 4.6.2 4.6.3 4.6.4
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pin Configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Basic Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Clock and Data Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Input Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Jitter Attenuator and Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Basic Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Output Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Local Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Remote Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Bypass Jitter Attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Receiver Loss of Signal Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Master/Slave Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Reset with CS Pin Fixed to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Reset Using CS Pin to Latch Programming (a controller is used) . . . . . . . . .26 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Electrical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Delay Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Delay from XDIP/XDIN to XL1/XL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Delay from RL1/RL2 to RDOP/RDON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Recommended Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Dual Rail Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 System Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 XTAL Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
3
Semiconductor Group
PEB 22320
4.7 4.8 5
Pulse Templates - Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Overvoltage Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
IOM(R), IOM(R)-1, IOM(R)-2, SICOFI(R), SICOFI(R)-2, SICOFI(R)-4, SICOFI(R)-4C, SLICOFI(R), ARCOFI(R) , ARCOFI(R)-BA, ARCOFI(R)-SP, EPIC(R)-1, EPIC(R)-S, ELIC(R), IPAT(R)-2, ITAC(R), ISAC(R)-S, ISAC(R)-S TE, ISAC(R)-P, ISAC(R)-P TE, IDEC(R), SICAT(R), OCTAT(R)-P, QUAT(R)-S are registered trademarks of Siemens AG. MUSACTM-A, FALCTM54, IWETM, SARETM, UTPTTM, ASMTM, ASPTM are trademarks of Siemens AG. Purchase of Siemens I2C components conveys a license under the Philips' I2C patent to use the components in the I2C-system provided the system conforms to the I2C specifications defined by Philips. Copyright Philips 1983.
Semiconductor Group
4
Primary Rate Access Clock Generator and Transceiver PRACT
Preliminary Data 1 Features
PEB 22320
CMOS
* ISDN line interface for 1544 and 2048 kbit/s (T1 and CEPT) * Data and clock recovery * Transparent to ternary codes * Low transmitter output impedance for a high return loss with reasonable protection resistors (CCITT G.703 requirements for the line input return loss P-LCC-44 fulfilled) * Adaptively controlled receiver threshold * Programmable pulse shape for T1 applications * Jitter specifications of CCITT I.431 and BELLCORE TR-NWT-000499 publications met * Wander and jitter attenuation * Jitter tolerance of receiver: 0.5 UI s * Implements local and remote loops for diagnostic purposes * Monolithic line driver for a minimum of external components * Low power, reliable CMOS technology * Loss of signal indication for receiver * Clock generator for system clocks Type PEB 22320 N Ordering Code Q67100-A6059 Package P-LCC-44 (SMD)
The Primary Rate Access Clock Generator and Transceiver PRACT (PEB 22320) is a monolithic CMOS device which implements the analog receive and transmit line interface functions to primary rate PCM carriers. It may be programmed or hard wired to operate in 1.544-Mbit/s (T1) or 2.048-Mbit/s (CEPT) carrier systems. The PRACT recovers clock and data using an adaptively controlled receiver threshold. It will meet the requirement of CCITT I.431 and Bellcore TR-NWT-000499 Issue 5, December 1993 (Transport System Generic Requirements) in case of pulse shape, jitter tolerance and jitter transfer characteristic.
Semiconductor Group
5
04.95
PEB 22320
Features Specially designed line interface circuits simplify the tedious task of protecting the device against overvoltage damage while still meeting the return loss requirements. The PRACT is suitable for use in a wide range of voice and data applications such as for connections of digital switches and PBX's to host computers, for implementations of primary ISDN subscriber loops as well as for terminal applications. The maximum range is determined by the maximum allowable attenuation. In the T1 case the PRACT's power consumption is mainly determined by the line length and type of the cable.
Semiconductor Group
6
PEB 22320
Features 1.1 Pin Configuration (top view)
CLK4M
CLK4M
JATT V DDR
6 FSC LS0 XTAL4 XTAL3 LS1 XTAL2 XTAL1 LS2 CLK16M CLK12M SYNC 7 8 9 10 11 12 13 14 15 16 17
5
4
3
2
1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 CLK2M RCLK RDON RDOP V SSD
PRACT PEB 22320
V SSR
RL2 V DD2
CLK2M
FSC
RL1
LL
V DDD
CS XCLK XDIP XDIN XTIP
18 19 20 21 22 23 24 25 26 27 28
V DDX
V DDX
XL1
N.C. V SSX
N.C.
MODE
XTIN
V SSX
XL2
RL
ITP04874
Semiconductor Group
7
PEB 22320
Features 1.2 Pin Definitions and Functions
Pin Definitions and Functions Pin No. 1 2 3 Symbol Input (I) Function Output (O) O I I Reference voltage for tapping the input transformer Line receiver pin 2 Local loopback: A high level selects the device for the local loopback mode. System clock 4.096 MHz inverted and non-inverted 8-kHz frame synchronization pulse inverted and non-inverted Line length select Crystal connection 12.352 MHz If an external clock generator is used and T1 mode is selected the PRACT works as a master. Line length select Crystal connection 16.384 MHz When an external clock is used, normally if the MODE pin is set high, the PRACT functions as a master. Line length select System clock 16.384 MHz System clock 12.352 MHz If a clock is detected at the SYNC pin the PRACT synchronizes to this clock (2.048 MHz for CEPT, 1.544 MHz for T1). (Please refer to table 3). Positive power supply for transmit subcircuits Line transmit pin 1 not connected I O Ground for transmit subcircuits Line transmit pin 2
VDD2
RL2 LL
4 5 6 7 8 9 10 11 12 13
CLK4M CLK4M FSC FSC LS0 XTAL4 XTAL3 LS1 XTAL2 XTAL1
O O O O I O I I O I
14 15 16 17
LS2
I
CLK16M O CLK12M O SYNC I
18, 19 20 21, 25 22, 23 24
VDDX
XL1 N.C.
I O
VSSX
XL2
Semiconductor Group
8
PEB 22320
Features Pin Definitions and Functions (cont'd) Pin No. 26 Symbol RL Input (I) Function Output (O) I Remote loopback: High level puts the device to the remote loopback mode. Master/Slave selection If the MODE pin is set to a low level the PRACT functions as a slave. (Please refer to table 3) Positive and negative test data inputs, active low, full bauded Positive and negative data inputs, active low, full bauded If the T1 mode is selected the XCLK is a clock output with a clock frequency of 1.544 MHz. Otherwise the XCLK is a clock input whose frequency is 2.048 MHz. (Please refer to table 3) Chip Select: A low level selects the PEB 22320 for a register write operation. Positive power supply for the digital subcircuits. Power ground supply for digital subcircuits. Receive data output positive and negative, fully bauded, active low. Receive clock refer to table 3. System clock 2.048 MHz inverted and non-inverted. Power ground supply for receive subcircuits. Positive power supply for the receive subcircuits. If the JATT pin is set to a low level the jitter attenuator is bypassed. Line receiver pin 1.
27
MODE
I
28 29 30 31 32
XTIN XTIP XDIN XDIP XCLK
I I I I I/O
33
CS
I
34 35 36 37 38 39 40 41 42 43 44
VDDD VSSD
RDOP RDON RCLK CLK2M CLK2M
I I O O O O O I I I I
VSSR VDDR
JATT RL1
Semiconductor Group
9
PEB 22320
Features 1.3 System Integration
Figure 1 shows the architecture of a primary access board for data transmission. It exhibits the following functions: - - - - - - - - - - Line Interface (PEB 22320, PRACT) Clock and Data Recovery (PEB 22320, PRACT) Jitter Attenuation (PEB 22320, PRACT) Clock Generation (PEB 22320, PRACT) Coding/Decoding (PEB 2035, ACFA) Framing (PEB 2035, ACFA) Elastic Buffer (PEB 2035, ACFA) Multichannel Protocol Controller (PEB 20320, MUNICH32) System Adaptation (PEB 20320, MUNICH32) P Interface (all devices)
MPU
Memory
PC Interface
MUNICH32 PEB 20320
TCLK/RCLK TSP/RSP
ACFA PEB 2035
SYPQ SCLK
PRACT PEB 22320
CLK4M FSC FSC CLK2M
4.096 MHz 8 kHz 8 kHz 2.048 MHz
ITS04875
Figure 1 Architecture of the PRACT
Semiconductor Group 10
PEB 22320
Functional Description 2 Functional Description
LL
MODE SYNC JATT
XTAL1, 2, 3, 4 XTIP Transmit XTIN Test Data
Local Loop
RL1 Receive Input RL2
Receiver
Clock & Data Recovery Loss of Signal Detection
RRCLK P N Jitter Attenuator & Clock Generator
XCLK (T1) System Clocks RCLK RDOP RDON
LOS
XL1 Transmit Output XL2
Driver D/A ROM Timing & Pulseshaper
Remote Loop
XDIP XDIN XCLK (CEPT)
ITB04876
LS0, 1, 2
RL
Figure 2 Functional Block Diagram of the PRACT
Semiconductor Group 11
PEB 22320
Functional Description 2.1 2.1.1 Receiver Basic Functionality
The receiver recovers data from the ternary coded signal at the ternary interface and outputs it as 2 unipolar signals at the dual rail interface. One of the lines carries the positive pulses, the other the negative pulses of the ternary signal. The signal at the ternary interface is received at both ends of a center-tapped transformer as shown in figure 3.
.
R L1 t 11
Line
R2 VDD 2
t2 t 12 R2
R L2
ITS00560
Figure 3 Receiver Configuration The transformer is center-tapped at the PRACT side. The recommended transmission factors for the different line characteristic impedances are listed in table 1. Table 1 Recommended Receiver Configuration Values Application Characteristic Impedances [] 100 28.7 T1 140 (ICOT) 39.2 120 60 CEPT 75 60
R2 (2.5%) [] t2 : t1 = t2 : (t11 + t12)
69:52 69:52 69:(26 + 26) 69:(26 + 26)
52:52 41:52 52:(26 + 26) 41:(26 + 26)
Wired in this way the receiver has a return loss
ar > 12 dB ar > 18 dB ar > 14 dB
for for for
0.025 fb 0.05 fb 1.0 fb
f f f
0.05 fb, 1.0 fb and 1.5 fb,
with fb being 2048 kHz. Thus it complies with CCITT G.703.
Semiconductor Group 12
PEB 22320
Functional Description The receiver is transparent to the logical 1's polarity and outputs positive logical 1's on RDOP and negative logical 1's on RDON. RDON and RDOP are active low and fully bauded. The comparator threshold to detect logical 1's and logical 0's is automatically adjusted to be 45% of the peak signal level. Provided the noise is below 10 V/Hz the bit error rate will be less than 10-7. 2.1.2 Clock and Data Recovery
An analog PLL extracts the internal recovered route clock RRCLK from the data stream received at the RL1 and RL2 lines. The PLL uses as a reference the system clock CLK16M for CEPT and CLK12M for T1 applications. The clock and data recovery is tolerant to long strings of consecutive zeros, because the data sampler will continuously sample data based on its last input. A block diagram of the clock and data recovery circuit is shown in figure 4.
Data Sampling
P Data N
Input Data derived from RL
1, 2
PD
Filter
VCO
RRCLK
CLK16M (CEPT) CLK12M (T1)
ITS04877
Figure 4 Clock and Data Recovery Circuit
Semiconductor Group 13
PEB 22320
Functional Description 2.1.3 Input Jitter Tolerance
The PRACT receiver's tolerance to input jitter complies to CCITT and Bellcore requirements for CEPT and T1 application. Figure 5 shows the curves of the different input jitter specifications stated above as well as the PRACT performance for the various line codes used at the S1/S2 interfaces. In figure 5 the curves show that the PRACT at low frequencies has more than 20 dB/ decade fall off, and at high frequencies is in a steady state of 0.5 UI (horizontal).
ITD06576
100 UI
Jitter Input Tolerance
10
TR-NWT 000499 Cat I TR-NWT 000499 Cat II PRACT CEPT PRACT T1 CCITT G.823
1
0.1
1
10
100
1000
10000 Jitter Frequency
Hz
100000
Figure 5 Comparison of Input Jitter Specification and PRACT Performance
Semiconductor Group
14
PEB 22320
Functional Description Table 2 Jitter Input Tolerance Frequency Hz 1 10 20 192.9 500 2400 6430 8000 10000 18000 20000 25000 40000 50000 100000 CCITT G.823 2.9 1.5 10 5 1.5 0.3 0.1 0.2 1.15 0.95 0.62 0.58 0.55 0.5 0.55 0.55 0.95 0.8 0.58 0.55 0.55 0.5 0.55 0.55 90 5.8 70 4.5 TR-NWT 000499 Cat I 5 TR-NWT 000499 Cat II 10 PRACT CEPT PRACT T1
0.1
0.3
2.1.4
Jitter Attenuator and Clock Generator
The jitter attenuator reduces wander and jitter in the recovered clock which are produced by the line-, clock- and data-recovery characteristics. The attenuator consists of one PLL with a tunable crystal oscillator and a 288-bit FIFO. To provide for T1 mode a 1.544-MHz clock (XCLK) and a 2.048-MHz clock (CLK2M) for the system, a second PLL is placed in series with the first one (refer to figure 6). If the JATT pin is set to low the FIFO is bypassed and the propagation delay from RL1, 2 to RDOP/RDON is reduced by the pass time of the FIFO. After loss of signal detection, the internal PLL is synchronized to the 2.048 MHz (CEPT) provided at the SYNC pin (1.544 MHz in the case of T1). If this SYNC pin is not connected or connected to logical zero, the PRACT switches automatically to master operating mode (refer to table 3). With the MODE pin a master selection is provided. That means if the MODE pin is set to high the master function is selected in which the VCO's of the jitter attenuator are centered ( 50 ppm of the crystal frequencies). If a clock is detected at the SYNC pin the PRACT automatically synchronized to this clock.
Semiconductor Group 15
PEB 22320
Functional Description The jitter attenuator meets the jitter transfer requirements of the Bellcore TR-NWT 000 499 and Rec. I.431 (refer to figure 7 and table 4). The amount of generated output jitter when no input jitter is shown in table 5.
JATT FIFO W RL1, 2 Clock & Data Recovery RRCLK MODE SYNC LOS 12.352 MHz P Data N Data R RDOP RDON RCLK
_ < 193
PD
VCO
12 MHz
8 kHz
_ < 256
_ < 193
_ <8
1.5 MHz (XCLK-T1)
T1 16.384 MHz
PD
VCO
16 MHz
_ < 256
_ <2
_ <4
8 kHz
2 MHz
4 MHz
ITB04879
Figure 6 Jitter Attenuator Block Diagram
Semiconductor Group 16
Pin JATT 16 M Crystal 16 M Crystal 16 M Crystal 16 M Crystal 16 M Crystal 16 M Crystal 16 M Crystal 16 M Crystal 16 M Crystal 16 M Crystal 16 M Crystal 16 M in 16 M Crystal 16 M Crystal 16 M Crystal 16 M Crystal 16 M Crystal 16 M Crystal 16 M Crystal 16 M Crystal 16 M Crystal 16 M Crystal 16 M Crystal 16 M in N.C. 16 M crystal sync. on XCLK 16 M crystal sync. on RRCLK 16 M crystal sync. freq. centered 16 M crystal sync. on SYNC 16 M crystal sync. on SYNC 16 M crystal sync. freq. centered 16 M in 16 M crystal sync. on XCLK 16 M crystal sync. on XCLK 16 M crystal sync. on XCLK 16 M crystal sync. on XCLK 16 M crystal sync. on XCLK N.C. 16 M in input (2 M from ACFA) output: 1.5 M sync. on RRCLK output: 1.5 M, freq. centered output: 1.5 M sync. on SYNC output: 1.5 M sync. on SYNC output: 1.5 M freq. centered output: 1.5 M sync. on XTAL3 input (2 M from ACFA) input (2 M from ACFA) input (2 M from ACFA) input (2 M from ACFA) input (2 M from ACFA) input (2 M from ACFA) RRCLK = Internal recovered route clock SYNC = 0: Input tied to low SYNC = 2 M: Input connected to 2 M SYNC = 1.5 M: Input connected to 1.5 M 16 M crystal sync. freq. centered input (2 M from ACFA) 16 M crystal sync. on SYNC input (2 M from ACFA) 16 M crystal sync. on SYNC input (2 M from ACFA) 16 M crystal sync. freq. centered input (2 M from ACFA) 16 M crystal sync. on RRCLK input (2 M from ACFA) =2 M =2 M =2 M =2 M =2 M =2 M =RRCLK =RRCLK =RRCLK =RRCLK =RRCLK =RRCLK =RRCLK =RRCLK =RRCLK =RRCLK =RRCLK =RRCLK 16 M crystal sync. on XCLK output: 1.5 M sync. on XTAL3 =1.5 M 16 M crystal sync. on XCLK output: 1.5 M freq. centered =1.5 M 16 M crystal sync. on XCLK output: 1.5 M sync. on SYNC =1.5 M 16 M crystal sync. on XCLK output: 1.5 M sync. on SYNC =1.5 M 16 M crystal sync. on XCLK output: 1.5 M, freq. centered =1.5 M 16 M crystal sync. on XCLK output: 1.5 M sync. on RRCLK =1.5 M
Int. Sig LOS
Pin SYNC
Pin MODE
Pin LS0..2
Pin XTAL3
Pin XTAL4
Pin XTAL1
Pin XTAL2
System Clocks 4M, 2M, 8K Derived from
Pin XCLK
Pin RCLK
1
0
X
0
T1
12 M Crystal
1
1
0
0
T1
12 M Crystal
1
1
1.5 M
0
T1
12 M Crystal
1
X
1.5 M
1
T1
12 M Crystal
Semiconductor Group
N.C. X X X X X X X X X X X X N.C X X X X X X X X X X X X
1
X
0
1
T1
12 M Crystal
1
X
X
X
T1
12 M in
1
0
X
0
CEPT
1
1
0
0
CEPT
1
1
2M
0
CEPT
Table 3 Clock and Synchronization Table
1
X
2M
1
CEPT
1
X
0
1
CEPT
1
X
X
X
CEPT
0
0
X
0
T1
12 M Crystal
17
12 M = 12.352 MHz 16 M = 16.384 MHz 4 M = 4.096 MHz 2 M = 2.048 MHz 1.5 M = 1.544 MHz
0
1
0
0
T1
12 M Crystal
0
1
1.5 M
0
T1
12 M Crystal
0
X
1.5 M
1
T1
12 M Crystal
0
X
0
1
T1
12 M Crystal
0
X
X
X
T1
12 M in
0
0
X
0
CEPT
0
1
0
0
CEPT
0
1
2M
0
CEPT
0
X
2M
1
CEPT
0
X
0
1
CEPT
0
X
X
X
CEPT
JATT = 1: Jitter attenuator enabled JATT = 0: Bypass jitter attenuator
Functional Description
PEB 22320
LOS = 0: Input above receiver threshold LOS = 1: Input below receiver threshold
MODE = 0 Slave mode selected MODE = 1: Master mode selected 8k = 8.0 kHz = don't care X N.C. = No Connection
PEB 22320
Functional Description
2 0 dB -10
ITD06577
Jitter Transfer Characteristics
-20
-30
-40
-50
CCITT G.735 CCITT I.431 TR-NWT 000499 Cat I to Cat I PRACT CEPT PRACT T1 0.1 1 10 100 1000 10000 Hz 100000
-60
Jitter Frequency
Figure 7 Jitter Attenuation Characteristics
Table 4 Jitter Transfer Characteristics Frequency Hz 0.3 1 3 10 30 40 100
Semiconductor Group 18
CCITT G. 735 CCITT I.431
TR-NWT 000499 Cat I to Cat II
PRACT CEPT
PRACT T1 0.00
0.00 0.5 0.5 0.10 - 20.00
- 20.00 - 40.00
PEB 22320
Functional Description Table 4 Jitter Transfer Characteristics (cont'd) Frequency Hz 200 250 300 350 400 9650 1000 1412 2500 3000 10000 15000 - 19.50 - 49.63 - 34.07 - 60.00 - -80.00 - 19.50 - 39.40 - 60.00 CCITT G. 735 CCITT I.431 TR-NWT 000499 Cat I to Cat II PRACT CEPT PRACT T1
Table 5 Generated Output Jitter Specification I.431 Measurement Filter Bandwidth Lower Cutoff 20 Hz 700 Hz Upper Cutoff 100 kHz 100 kHz 8 kHz 40 kHz 40 kHz broad band ETS 300 011 40 Hz 100 kHz Output Jitter (UI peak to peak) 0.125 0.02 0.02 0.025 0.025 0.05 0.11
PUB 62411 Dez. 90 10 Hz 8 kHz 10 Hz
Semiconductor Group
19
PEB 22320
Functional Description 2.2 2.2.1 Transmitter Basic Functionality
The transmitter transforms unipolar data to ternary (alternate bipolar) return to zero signals of the appropriate shape. The unipolar data is provided at XDIP (positive pulses) and XDIN (negative pulses), synchronously with the transmit clock XCLK. XDIP and XDIN are active low and full bauded. Data is sampled on the falling edge of the input clock (XCLK). The input clock (XCLK) must be derived from the (system) clocks generated by the PRACT. This ensures the recommended fixed relationship between XLCK and internal generated clock (4 times XCLK) for the pulse shaper. The transmitter includes a programmable pulse shaper to satisfy the requirements of the AT&T Technical Advisory # 34 at the cross connect point for T1 applications. The pulse shaper is programmed via the line length selection pins LS0, LS1 and LS2. For T1 application the line length selection supports both low capacitance cable with a characteristic line capacitance of C' 40 nF/km = 65 nF/mile (e.g. MAT, ICOT) and higher capacitance cable with a characteristic line capacitance of 40 nF/ km C' 54 nF/km (65 nF/mile C' 87 nF/mile) e.g. ABAM, PIC and PULP cables. This ensures that for various cable types the signal at the DSX-1 cross connect point complies with the pulse shape of the AT&T Technical Advisory # 34. The line length is selected programming the LS0, LS1 and LS2 pins as shown for typical values in table 6. Table 6 Line Length Selection LS2 0 0 0 0 1 1 1 1 LS1 0 0 1 1 0 0 1 1 LS0 0 1 0 1 0 1 0 1 CEPT T1/G.703 T1 T1 T1 T1 T1 T1 PIC/PULP Cable 24 AWG range/m - 0 20 60 110 140 210 270 - - - - - - - 50 80 130 200 230 290 320 ICOT Cable range/m* - 0 65 130 195 260 325 390 - - - - - - - 80 145 210 275 340 405 470
Note: * For ICOT-cable the characteristic impedance is 140 By selecting an all-zero code for LS0, LS1 and LS2 the PRACT can be adapted for CEPT applications.
Semiconductor Group
20
PEB 22320
Functional Description The pulse shape according to CCIT G.703 (1544-kbit/s interface) is achieved by using the same line length selection code as for the lowest T1 cable range. To switch the device into a low power dissipation mode, XDIP and XDIN should be held high. The transmitter requires an external step up transformer to drive the line. The transmission factor and the source serial resistor values can be seen in figure 8 and table 7 for the various applications.
R1
XL1
t 11 t2 R1
XL 2 Line
t 12
ITS00562
Figure 8 Transmitter Configuration Table 7 Transmitter Configuration Values Application Characteristic line impedance [] 100 26:69 4.3 T1 140 (ICOT) 120 26:69 6 26:52 15 CEPT 75 26:41 15
t11 : t2 = t12 : t2 R1 ( 2.5%) []
Wired in this way the transmitter has a return loss
ar > 8 dB ar > 14 dB ar > 10 dB
for for for
0.025 fb 0.05 fb 1.0 fb
f f f
0.05 fb, 1.0 fb and 1.5 fb,
with fb being 2048 kHz (CEPT applications). A termination resistor of 120 is assumed. In T1 applications the return loss is higher than 10 dB. Please note, that the transformer ratio at the receiver is half of that at the transmitter. The same type of transformer can thus be used at the receiver and at the transmitter. At the transmitter the two windings are connected in parallel, at the receiver in series. Thus, unbalances are avoided.
Semiconductor Group
21
PEB 22320
Functional Description 2.2.2 Output Jitter
In the absence of any input jitter the PRACT generates the output jitter, which is specified in table 5. Note: The generated output jitter on the line is the same as the output jitter of the system clocks. 2.3 Local Loopback
The local loopback mode disconnects the receive lines RL1 and RL2 from the receiver. Instead of the signals coming from the line the data provided at XTIP and XTIN are routed through the receiver. The XDIN and XDIP signals continue to be transmitted on the line. The local loopback occurs in response to LL going high. 2.4 Remote Loopback
In the remote loopback mode the clock and data recovered from the line inputs RL1 and RL2 are routed back to the line outputs XL1 and XL2 via the transmitter. As in normal mode they are also output at RDOP and RDON. XDIP and XDIN are disconnected from the transmitter. The remote loopback mode is selected by a high RL signal. 2.5 Bypass Jitter Attenuator
If the JATT pin is set to low the jitter attenuator (FIFO) is bypassed and the propagation delay from the line to the dual rail interface is reduced by the path time of the FIFO. Also in this mode the jitter in the system clocks (CLK2M, CLK4M, FSC) is attenuated. 2.6 Microprocessor Interface
The PRACT is fully controlled by six parallel data lines (LS0, LS1, LS2, LL, RL and JATT) and one control line (CS). To adapt the device to a standard microprocessor interface the low state of CS is decoded from the microprocessor address, CS, WR and ALE lines. To hardwire the chip, CS must be fixed to ground. 2.7 Receiver Loss of Signal Indication
In the case that the signal at the line receiver input (pins RL1, RL2) becomes smaller than Vin 0.3 VOP loss of signal is indicated. This voltage value corresponds to a line attenuation of about 14 dB in the CEPT case. This is performed by turning both signals RDOP, RDON after at least 32 bits simultaneously to 5 V, i.e. a logical 0 on both lines. The following ACFA processes this indication for the system. In this mode the PRACT synchronizes to the clock at the SYNC pin.
Semiconductor Group
22
PEB 22320
Functional Description 2.8 Master/Slave Selection
If the MODE pin is set to high and the SYNC pin is not connected or connected to VSS the PRACT works as a master for the system. The VCO's of the jitter attenuator are centered ( 50 ppm of the crystal frequencies) and the system clocks are stable (divided from the VCO frequencies). If a clock (2.048 MHz for CEPT, 1.544 MHz for T1) is detected at the SYNC pin the PRACT synchronizes automatically to this clock. In master mode, the PRACT is independent from the receiver loss of signal detection. Note: The MODE pin can not be controlled by the P interface and requires CMOS levels as input signals. It must always be connected either to VDD or VSS. A voltage of 2.5 V at the MODE Pin switch the PRACT into test mode.
Semiconductor Group
23
PEB 22320
Operational Description 3 3.1 Operational Description Reset
After power up resetting the device is necessary to synchronize the internal circuitries. After reset a stabel RCLK is available after 65536 clock cycles. This results in 32 ms in CEPT mode and 42.5 ms in T1 mode. A reset can be performed by two ways. 3.1.1 Reset with CS Pin Fixed to VSS
In this reset operation the CS pin is normally hardwired to VSS. Before giving a reset the operational mode has to be selected (CEPT, T1) by setting the pins LS2, LS1, LS0 to 000 for CEPT-application, to 001 for NTT-application or 001 ... 111 for T1 application. A reset is made by simultaneously setting both RL and LL to high (CS = 0) for at least 1 s. Reset will be initiated on the falling edge of RL or LL, the one that falls first. The following figures explain the procedure in some examples.
CS LS2 LS1 LS0 RL LL 1s 1. 1. Start of Reset 2. End of Reset 2.
t
ITD04881
Figure 9 Resetting PRACT for CEPT Applications
Semiconductor Group
24
PEB 22320
Operational Description
CS LS2 LS1 LS0 RL LL JATT
t
1. 2.
1. Start of Reset 2. End of Reset and local loop is initiated
ITD04882
Figure 10 Resetting PRACT for CEPT Applications and Setting Local Loop with Jitter Attenuation
CS LS2 LS1 LS0 RL LL
t
1. 2. 3.
1. Start of Reset 2. End of Reset, regular operation in T1 Mode 3. Remote loop is initiated
ITD04883
Figure 11 Resetting PRACT for T1 Applications (max. line length selected) and Setting Remote Loop Note: If the PRACT is initiated for T1 applications the line length selection can be changed without a new reset.
Semiconductor Group
25
PEB 22320
Operational Description 3.1.2 Reset Using CS Pin to Latch Programming (a controller is used)
Reset is done by setting the pins RL and LL to logical 1 for at least 1 s and latching these values into PRACT by a rising edge at pin CS. The selection of CEPT, T1 applications is achieved by setting the pins LS2, LS1, LS0 simultaneously with the reset to 000 for CEPT application or a T1 line length code (001 ... 111 see table 6). The logical level of the RL, LL, LS2, LS1, LS0, JATT input parts are latched with the rising edge of the CS. Refer to figure 20. The following figures explain the procedure in some examples.
CS RL JATT LL LS0, 1, 2 1 s 1. 2.
ITD04884
t
1. Start of Reset 2. End of Reset, Regular operation in CEPT Mode
Figure 12 Resetting PRACT for CEPT Applications and Jitter Attenuation
CS RL LL LS0, 1, 2
t
1. 1. Start of Reset 2. End of Reset and setting remote loop 2.
ITD04885
Figure 13 Resetting PRACT for CEPT Application and Setting Remote Loop
Semiconductor Group 26
PEB 22320
Operational Description
CS RL LL LS0, 1, 2 xxx
001
xxx
001
xxx
xxx
010
xxx
t
1. 2. 3.
1. Start of Reset 2. End of Reset and setting line length code, Regular operation in T1 Mode 3. Changing line length code, Regular operation in T1 Mode with changed line length code
ITD04886
Figure 14 Resetting PRACT for T1 Applications and Changing Line Length Code
CS RL LL LS0, 1, 2 xxx
111
xxx
111
xxx
t
1. 1. Start of Reset 2. End of Reset and setting local loop and line length code 2.
ITD04887
Figure 15 Resetting PRACT for T1 Application and Setting Local Loop
3.2
Operation
The PRACT is in normal operation as soon as the reset phase is finished. The CS pin is activated again only when PRACT is reprogrammed (for example setting a loop or changing line length code). That means CS pin could be kept high for normal operation.
Semiconductor Group
27
PEB 22320
Electrical Specification 4 4.1 Electrical Specification Absolute Maximum Ratings Symbol VS TA Tstg Limit Values Unit
Parameter Voltage on any pin with respect to ground Ambient temperature under bias Storage temperature
- 0.4 to VDD + 0.4 V 0 to 70 - 65 to 125 C C
4.2 4.2.1
Delay Times Delay from XDIP/XDIN to XL1/XL2
The delay from XDIP/XDIN to XL1,XL2 is 770 ns in T1 mode and 860 ns in CEPT mode. This relates to the falling edge of the XCLK and the leading edge of XL1 or XL2. 4.2.2 Delay from RL1/RL2 to RDOP/RDON
The delay from RL1/RL2 to RDOP/RDON is given with 700 ns in T1 mode and 540 ns in CEPT mode. This relates to the leading edge of the RL1 or RL2 to the falling edge of RDOP or RDON.
Semiconductor Group
28
PEB 22320
Electrical Specification 4.3 DC Characteristics
TA = 0 to 70 C; VDD = 5 V 5%, VSS = 0 V
DC Characteristics Parameter L-input voltage H-input voltage L-output voltage H-output voltage H-output voltage Input leakage current Output leakage current Peak voltage of a mark (CEPT) Peak voltage of a mark (T1) Symbol Limit Values min. max. 0.8 0.45 2.4 V V V V 1 A VDD + 0.4 V All pins except MODE, RLx, XLx XTALx, VDD2, SYNC - 0.4 2.0 Unit Test Condition Pins
VIL VIH VOL VOH VOH ILI ILO VXCEPT VXT1
VDD -
0.5
IOL = 2 mA IOH = - 400 A IOH = - 100 A
0 V < VIN < VDD to 0V 0 V < VOUT < VDD to 0V
2.7 1.8
3.3 3.4
V V
wired according figure 8 and table 7 T1 application: depending on line length XL1, XL2
Transmitter output RX impedance Transmitter output IX current
0.3 50 150
mA mA CEPT application T1 application: depending on line length RL1, RL2
Receiver input peak voltage of a mark Loss of signal threshold Receiver input threshold Voltage at VDD2
VR1)
0.4
2.5
V
VLOS VRTH VDD2
0.3 45 2.4 2.6
V % V
Semiconductor Group
29
PEB 22320
Electrical Specification DC Characteristics (cont'd) Parameter L-input voltage H-input voltage Input leakage current Operational power supply current Symbol Limit Values min. max. 1.0 V V A mA mA 0 V VIN VDD to 0V CEPT application T1 application, min value for all zeros, max value for all ones and max. line length for T1 appl. MODE, SYNC - 0.4 4.0 Unit Test Condition Pins XTAL1, XTAL2, XTAL3, XTAL4
VXTALIL VXTALIH IXTALI ICC
VDD +
0.4 1
40 55
110 190
L-input voltage H-input voltage Input leakage current
VIL VIH ILI1 ILI2 ILI3 ILI4
- 0.4 4.0
0.8
V V A A A A
VDD +
0.4 800 100 800 200
VIL = 0.8 V VIL = 0.1 V VIH = 4 V VIH = VDD
1)
Measured against VDD2
4.4
Characteristics
TA = 25 C; VDD = 5 V 5 %, VSS = 0 V
Parameter Input capacitance Output capacitance Input capacitance Output capacitance Symbol min. Limit Values max. 10 15 7 20 pF pF pF pF all except RLx, XLx, XTALx all except RLx, XLx, XTALx RLx XLx Unit Pins
CIN COUT CIN COUT
Semiconductor Group
30
PEB 22320
Electrical Specification 4.5 Recommended Oscillator Circuits
XTAL1 (XTAL3)
C L = 14 pF (4 pF)
16.384 MHz (12.352 MHz)
XTAL1 (XTAL3)
PRACT
XTAL2 (XTAL4)
PRACT
XTAL2 (XTAL4)
External Oscillator Signal 16.384 MHz (12.352 MHz) N.C.
14 pF Crystal Oscillator mode (slave mode/ master mode) Driving from external source (master mode)
ITS04888
Figure 16 Oscillator Circuits In CEPT mode if an external source is connected to XTAL1, the PRACT works, independent of the MODE pin, in master mode. In T1 mode if an external source is connected to XTAL3, the PRACT works, independent of the MODE pin, in master mode. This operational mode requires a crystal (16.384 MHz) at pins XTAL1 and XTAL2. The frequency is locked to the external source. The jitter attenuator requires unique performance specifications for the crystals. The following typical crystal parameters will meet this specifications: - Motional capacitance - Shunt capacitance - Load capacitance - Resonance resistance C1 = 25 fF min C0 = 7 pF max CL = 18 pF typ, f0 = 16.384 MHz CL = 10 pF typ, f0 = 12.352 MHz Rr 25
Semiconductor Group
31
PEB 22320
Electrical Specification PRACT Tuning Range 16.384 MHz PLL Crystal specified for CL = 18 pF
150 df ppm f 0 100
ITD06578
50
0
-50
-100
-150 14
16
18
20
22
24
pF
26
CL
Figure 17 16.384-MHz Crystal Tuning Range
Semiconductor Group
32
PEB 22320
Electrical Specification PRACT Tuning Range 12.352 MHz PLL Crystal specified for CL = 10 pF
250 ppm df 200 f0 150 100 50 0 -50 -100 -150 -200 -250 6 8 10 12 14 16 pF
ITD06579
18
CL
Figure 18 12.352-MHz Crystal Tuning Range
Semiconductor Group
33
PEB 22320
Electrical Specification 4.6 AC Characteristics
TA = 0 to 70 C; VDD = 5 V 5 %
2.4 2.0 Test Points 0.8 0.45 0.8 2.0 Device Under Test
C Load = 150 pF
ITS00621
Figure 19 Input/Output Waveforms for AC Tests Except from the line interface, inputs are driven at 2.4 V for a logical 1 and 0.4 V for a logical 0. Timing measurements are made at 2.0 V for a logical 1 and at 0.8 V for a logical 0. AC testing input/output waveforms are shown in figure 19. 4.6.1 Dual Rail Interface
RDOP, RDON, XDIP, XDIN, XTIP, XTIN are active low.
t CPR t CPRH
RCLK
t CPRL
t DROS
t DROH
RDOP, RDON
t CPX t CPXH
XCLK
t CPXL
t DRIS
XDIP, XDIN XTIP, XTIN
t DRIH
ITT04889
Figure 20 Timing of the Dual Rail Interface
Semiconductor Group 34
PEB 22320
Electrical Specification Parameter Symbol min. RCLK clock period RCLK clock period low RCLK clock period high Dual rail output setup Dual rail output hold XCLK clock period XCLK clock period low XCLK clock period high Dual rail input setup Dual rail input hold Limit Values PCM 30 max. PCM 24 min. 260 260 260 260 typ. 648 250 250 25 25 max. ns ns ns ns ns ns ns ns ns ns typ. 648 Unit
tCPR tCPRL tCPRH tDROS tDROH tCPX tCPXL tCPXH tDRIS tDRIH
typ. 488 200 200 200 200 typ. 488 200 200 25 25
Semiconductor Group
35
PEB 22320
Electrical Specification 4.6.2 System Clock Interface
t CP16L
CLK16M
t CP16
t CP16H
t CP4L
CLK4M CLK4M
t CP4 t CP4H
t CP2 t CP2L
CLK2M CLK2M
t CP2H
t SS
FSC FSC
t SH
t CP12L
CLK12M
t CP12
t CP12H
t CP15 t CP15L
XCLK (T1)
ITT04890
t CP15H
Figure 21 Timing of the System Clock Interface
Semiconductor Group 36
PEB 22320
Electrical Specification System Clock Interface Timing Parameter Values Parameter CLK16M period 16 MHz CLK16M period 16 MHz low CLK16M period 16 MHz high CLK4M period 4 MHz CLK4M period 4 MHz low CLK4M period 4 MHz high CLK2M period 2 MHz CLK2M period 2 MHz low CLK2M period 2 MHz high FSC setup time FSC hold time CLK12M period 12 MHz CLK12M period 12 MHz low CLK12M period 12 MHz high XCLK period 1.5 MHz XCLK period 1.5 MHz low XCLK period 1.5 MHz high Symbol Limit Values min. max. typ. 61 20 20 typ. 244 110 110 typ. 488 220 220 110 240 typ. 81 30 30 typ. 648 300 300 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
tCP16 tCP16L tCP16H tCP4 tCP4L tCP4H tCP2 tCP2L tCP2H tSS tSH tCP12 tCP12L tCP12H tCP15 tCP15 L tCP15 H
Semiconductor Group
37
PEB 22320
Electrical Specification 4.6.3 Microprocessor Interface
t CYC t WC
CS
t DW
DATA (JATT, RL, LL, LS0, 1, 2)
t WD
ITT04891
Figure 22 Timing of the Microprocessor Interface
Parameter CS pulse width Data setup time to CS Data hold time from CS Cycle time
Symbol
Limit Values min. max. - - - 60 35 10 120
Unit ns ns ns ns
tWC tDW tWD tCYC
Semiconductor Group
38
PEB 22320
Electrical Specification 4.6.4 XTAL Timing
tP t WH
XTAL1 XTAL3 3.5 V 0.8 V
ITT04892
t WL
Figure 23 Timing of XTAL1/XTAL3 XTAL1/XTAL3 Timing Parameter Values Parameter Clock period of crystal/ clock High phase crystal/clock Symbol Limit Values min. typ. 61 81 20 30 20 30 max. ns ns ns XTAL1 XTAL3 XTAL1 XTAL3 XTAL1 XTAL3 Unit Condition
tP tWH
Low phase of crystal/clock tWL
Note: If an external clock is used the PRACT works as a master. Please refer to Pin Definitions.
Semiconductor Group
39
PEB 22320
Electrical Specification 4.7 Pulse Templates - Transmitter
The PRACT meets both CCITT and T1 pulse template requirements.
269 ns (244 + 25) 194 ns (244 - 50)
V=100 %
10 % 10 % 20 % 20 %
Nominal Pulse
50 % 244 ns 219 ns (244 - 25)
10 % 10 % 10 % 10 %
ITD00573
0%
Figure 24 Pulse Template at the Transmitter Output for CEPT Applications
Semiconductor Group 40
20 %
488 ns (244 + 244)
PEB 22320
Electrical Specification
Normalized Amplitude
V = 100 %
50 %
0
-50 % 0 250 500 750 1000 ns
ITD00574
t
Figure 25 T1 Pulse Shape at the Cross Connect Point Table 8 T1 Pulse Template Corner Points at the Cross Connect Point Maximum Curve (0 (250, (325, (325, (425, (500, (675, (725, (1100, (1250, 0.05) 0.05) 0.80) 1.15) 1.15) 1.05) 1.05) - 0.07) 0.05) 0.05) (0, (350, (350, (400, (500, (600, (650, (650, (800, (925, (1100, (1250, Minimum Curve - 0.05 - 0.05) - 0.50) 0.95) 0.95) 0.90) 0.50) - 0.45) - 0.45) - 0.20) - 0.05) - 0.05)
Semiconductor Group
41
PEB 22320
Electrical Specification
V
3.0 1.5 0
50 ns
0.7 0.7
50 ns
0.3
3T T 8 4 0
1.2
T 8
-
T 4
3T 8
T 2
T = 1/1544
kHz
ITD00575
Figure 26 Pulse Shape According to CCITT G.703
4.8
Overvoltage Tolerance
To prevent the PRACT from being damaged by overvoltage (i.e. from lightning), external devices like diodes or resistors have to be connected to one or both sides of the line interface transformers. Thus, overvoltage peaks are cut off. However, some residual overvoltage may remain. The PRACT simplifies the task of designing external protection circuits. Its transmitter exhibits a low line impedance so that reasonable external resistors can be connected to the line outputs. Figure 8 with the element values of table 7 gives an example of how an overvoltage protection against residual overvoltages at the ternary interface can be accomplished. The solution shown also meets the stated return loss requirements. A similar consideration applies to the receiver. The resistors R2 of figure 3 provide protection against residual overvoltages by attenuating voltages of both polarities across RL1 and RL2. The maximum input current allowed to reach the PRACT pins under overvoltage conditions is given as a function of the width of a rectangular input current pulse according to figure 27. Figure 29 shows the curve of the maximum allowed input current across the pins RL1 and RL2, figure 28 across the pins XL1 and XL2.
Semiconductor Group
42
PEB 22320
Electrical Specification
FALC TM -54
p
t t WI
ITS04893
Condition: All other pins grounded
Figure 27 Measurement of Overvoltage Stress
P
A 100 50 10 5 1 0.5 10 dB/Decade _ Ri < 2
2x10 -1
10 -9
10 -6
10 -3 10 -2 1
t WI
s
ITD00578
Figure 28 Tolerated Input Current at the XL1, XL2 Pins
Semiconductor Group 43
PEB 22320
Electrical Specification
P
A 20 10 10 dB/Decade _ R i < 300
1 6x10
-1
10 -1 2x10 -1 10 -10 10 -9 10 -6 10 -4 10 -3
t WI
s 1
ITD00577
Figure 29 Tolerated Input Current at the RL1, RL2 Pins
Semiconductor Group
44
PEB 22320
Package Outlines 5 Package Outlines
Plastic Package, P-LCC-44 (SMD) (Plastic Leaded Chip Carrier)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 45
Dimensions in mm
GPL05102

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